I. Field of the Disclosure
The technology of the disclosure relates generally to processing of pipelined computer instructions in central processing unit (CPU)-based systems.
II. Background
The central processing unit (CPU) of virtually every digital computer includes a small number of storage areas known as registers. Each register can provide local storage for a variety of data. Examples include operands to be manipulated by the CPU, memory addresses to be accessed by the CPU, and results of calculations that are performed by the CPU. Because the registers are physically located within the CPU itself, the CPU can store data in the registers and retrieve data from the registers much more quickly than the CPU can access cache memory or the computer's main memory.
The advent of “instruction pipelining” in modern computer architectures has made complex use of computer registers. Instruction pipelining is a processing technique whereby a throughput of computer instructions being processed by a CPU may be increased by splitting the processing of each instruction into a series of steps. The instructions are executed in a “processor pipeline” composed of multiple stages, with each stage carrying out one of the steps for each of a series of instructions. As a result, in each CPU clock cycle, various steps of the multiple instructions can be evaluated in parallel, resulting in improved utilization of CPU resources and faster execution times of computer applications.
However, the use of instruction pipelining may introduce unexpected consequences if dependencies exist between one or more instructions. For example, a first instruction in a processing pipeline may not be guaranteed to complete execution before a subsequent instruction begins execution. If the subsequent instruction depends on a result of the execution of the first instruction, a condition known as a “read-after-write hazard” may arise. To resolve the read-after-write hazard, the CPU may “stall” the pipeline (i.e., introduce an intentional delay into the pipeline to allow the first instruction to complete execution).
One particular instance in which the possibility of a read-after-write hazard may arise is during generation of constant values for storage in a register. A constant value may be generated through the use of an instruction in conjunction with an “immediate value” (i.e., a value that is encoded directly in the instruction and that is used as numeric data when the instruction is executed) to write the immediate value into the register. The limitations of a computer's architecture may impose restrictions on the size of an immediate value that can be moved to a register using a single instruction. Because some bits of the single instruction are used for data such as the instruction type and the register to which the immediate value is to be written, an immediate value must be smaller than the size of the instructions in the computer's instruction set. Consequently, generation of a 32-bit constant using a 32-bit instruction set, for instance, may entail the execution of at least two separate instructions. Because the subsequent instruction(s) are dependent upon the execution of the preceding instruction(s), a read-after-write hazard may be encountered with the associated risks of stalling the pipeline in which the instructions are executing. Moreover, while other techniques exist for mitigating the chance of a read-after-write hazard (such as allowing an instruction to overwrite only a portion of a register), they may introduce additional, undesirable complexities to the computer's architecture.
Accordingly, it may be desirable to reduce the risk of a read-after-write hazard associated with immediate value, write-based instructions, without having to stall the pipeline.